1. Technical Field
The present invention relates to multi-chip packages, and more particularly, to a multi-chip package which can minimize the parasitic load of a package pin by adjusting the number of chips coupled to the package pin.
2. Description
In recent years, multi-chip package techniques for incorporating several memory chips into a single package have been widely used to increase memory capacity. However, in typical multi-chip packages, a parasitic load of a package pin is proportional to the number of embedded memory chips. An increased parasitic load impedes high-speed transmission of signals input to the package pin. Accordingly, it is imperative for the multi-chip packages to reduce the parasitic load of the package pin to at least the level of the parasitic load of a single chip.
FIG. 1 is a diagram of a memory bus coupled to N memory modules, each of which includes a memory device.
Referring to FIG. 1, N memory modules MM1, MM2, . . ., and MMN are mounted on N memory slots SLOT1, SLOT2, . . . , SLOTN. Each of the memory modules MM1, MM2, . . . , and MMN includes a memory device M1, M2, . . . , and MN, respectively. In FIG. 1, C represents an input capacitance of each of the memory modules MM1, MM2, . . . , and MMN.
High-performance memory systems are required to connect more memory per channel and simultaneously transmit signals faster. The amount of memory connected to one channel is limited in order to transmit signals at high speed.
The memory bus of FIG. 1 has an input capacitance of N×C, and the capacitance has the same effect as a load on signal transmission. That is, as N increases, it becomes difficult to transmit signals at high speed. In a typical stub-type memory bus, the number of slots for mounting memory modules is limited to four or less.
In general, while the number of memory slots is limited, to secure maximum memory capacity a memory module is manufactured by stacking several packages, or mounting several chips in a single package.
However, even if a stacked package or a multi-chip package is used, in a case that requires an increased transmission rate of signals, it is still difficult to transmit signals at high speed due to the entire load of signal transmission lines. Also, to secure signal compatibility, packages such as multi-chips may not be used and the number of memory slots is more strictly limited.
FIG. 2 is a diagram of a memory bus, in which the number of memory slots is limited to two.
Referring to FIG. 2, a first memory module MM1 includes two multi-chip devices M1 and M2, each of which includes two semiconductor chips. A second memory module MM2 includes two multi-chip devices M3 and M4, each of which also includes two semiconductor chips. Thus, the memory bus of FIG. 2 has an input capacitance of 8×C.
FIG. 3 is a diagram illustrating signal compatibility in relation to operations of the memory bus of FIG. 2.
In FIG. 3, the horizontal axis is the time axis and the vertical axis is the voltage axis.
It can be seen that both the first and second slots SLOT1 and SLOT2 exhibit low signal compatibility for write and read operations.
FIG. 4 is a diagram of a memory bus, in which the number of memory chips is reduced when compared to the memory module of FIG. 2.
FIG. 5 is a diagram illustrating signal compatibility in relation to operations of the memory bus of FIG. 4.
Referring to FIG. 4, a first memory module MM1 includes only two semiconductor chips M1 and M2, and a second memory module MM2 also includes only two semiconductor chips M3 and M4. Thus, the memory bus of FIG. 4 has an input capacitance of 4×C.
Referring to FIG. 5, when the input capacitance of the memory bus in FIG. 4 is reduced compared to the input capacitance of the memory bus in FIG. 2, then the signal compatibility is improved. Therefore, minimizing the parasitic load of a package pin improves the signal compatibility in a memory bus where signals are transmitted at high speed.
The present invention provides a multi-chip package which can minimize the parasitic load of a package pin and improve signal compatibility in a memory bus using memory modules supporting multiple semiconductor chips.
In accordance with an aspect of the present invention, there is provided a multi-chip package, comprising first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other.
The internal pads are coupled to each other via a common pad installed at a substrate. The input/output pad of the first semiconductor chip is bonded to an external pin of the multi-chip package.
Each of the first through (N−1)th semiconductor chips includes a delay circuit for receiving the input/output signal at the moment the internal circuit of the Nth semiconductor chip receives the input/output signal.
In accordance with another aspect of the present invention, there is provided a multi-chip package, comprising first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The first through Nth semiconductor chips include direct input/output pads, which directly receive predetermined external signals input via corresponding pins of the multi-chip package.
The internal pads are coupled to each other via a common pad installed at a substrate. The input/output pad of the first semiconductor chip is bonded to an external pin of the multi-chip package.
Each of the first through (N−1)th semiconductor chips includes a delay circuit for receiving the input/output signal at the moment the internal circuit of the Nth semiconductor chip receives the input/output signal. The external signals are transmitted at a lower speed than the input/output signals.
In accordance with still another aspect of the present invention, there is provided a multi-chip package, comprising first through Nth semiconductor chips, each of which includes first through Nth (N is a natural number) input/output pads, first through Nth input/output drivers coupled to the input/output pads, and an internal circuit. Each of the first through Nth semiconductor chips includes first through Nth internal pads for coupling the internal input/output drivers and the internal circuit. The first through Nth internal pads of the first semiconductor chip are coupled to the corresponding first through Nth internal pads of the second through Nth semiconductor chips. Predetermined first through Nth input/output signals are received via corresponding pins of the multi-chip package. An input/output signal for each semiconductor chip is received by the corresponding input/output pad. The first through Nth semiconductor chips indirectly receive the other input/output signals via the corresponding internal pads, which are coupled to each other.
The first through Nth internal pads are coupled to each other via first through Nth common pads installed at a substrate. The first through Nth semiconductor chips include delay circuits for controlling delay times of the input/output signals, such that the input/output signals received by the first through Nth semiconductor chips are simultaneously input to the internal circuit.
The first through Nth semiconductor chips further include direct input/output pads, which directly receive predetermined external signals input via corresponding pins of the multi-chip package. The external signals are transmitted at a lower speed than the input/output signals.
In accordance with further another aspect of the present invention, there is provided a multi-chip package, comprising first through Nth semiconductor chips, each of which includes a plurality of input/output pads, a plurality of input/output drivers coupled to the input/output pads, and an internal circuit. Each of the first through Nth semiconductor chips includes internal pads. The total number of internal pads equals that of the internal input/output drivers, the internal pads used for coupling the input/output drivers and the internal circuit. The plurality of internal pads of the first semiconductor chip are coupled to the plurality of internal circuits corresponding thereto of the second through Nth semiconductor chips. Among predetermined first through Mth (M>N, M is a natural number) input/output signals received via pins of the multi-chip package, the input/output signals are divided and transmitted directly to the input/output pads of the first through Nth semiconductor chips. The first through Nth semiconductor chips indirectly receive the other input/output signals via the corresponding internal pads, which are coupled to each other.
The plurality of internal pads are coupled to each other via a plurality of corresponding common pads installed at a substrate. The first through Nth semiconductor chips include delay circuits for controlling delay times of the input/output signals, such that the input/output signals received by the first through Nth semiconductor chips are simultaneously input to the internal circuit.
The first through Nth semiconductor chips further include direct input/output pads, which directly receive predetermined external signals input via corresponding pins of the multi-chip package. The external signals are transmitted at a lower speed than the input/output signals.